On the Effects of Cumulative SEUs in FPGA-based Systems

Authors

Abstract

Field programmable hardware, namely FPGA, is increasingly being used in critical applications. These state-of- the-art devices are based on SRAM memory, which is very sensitive to faults. However, due to the characteristics of such devices, errors on memory cells usually have no immediate effect on the implemented system’s outputs, meaning that they can be either harmless or eventually cause a late system failure due to a long latency. This is the reason why some manufacturers, such as Xilinx, added a scrubbing capability to some FPGAs, allowing the designers to periodically reprogram the memory cells, wiping any latent error. In this paper we investigate how useful could this scrubbing be, by measuring the error latencies in SRAM memory cells affecting a PID-based cruise control system. Errors are emulated through fault injection using the Fault Injector for Reconfigurable Embedded Devices – FIRED, through Partial Dynamic Reconfiguration. The results show that about half of the system failures were due to errors with long latencies, which could be avoided by reprogramming the FPGA. We have also observed an interesting phenomenon: some failures are due to the combination of faults that, taken in isolation, would have been innocuous to the system.

Keywords

dependability, SEU, FPGA, fault injection, embedded systems

Subject

Hardware Dependability

Conference

12th European Dependable Computing Conference (EDCC 2016) 2016