Using Failure Prediction to Improve FPGA Scrubbing

Authors

Abstract

Programmable hardware devices, specifically FPGAs, are increasingly being used in critical applications. State- of-the-art devices use SRAM memory for configuration purposes, which is very sensitive to faults. Previous studies have shown that, the vast majority of the generated errors have a high latency, and that some failures are due to the accumulation of errors. To overcome these threats, manufacturers, such as Xilinx, allow the designer to periodically refresh the configuration memory cells, through a mechanism known as scrubbing. The decision on its use is based on system availability requirements, and designer knowledge about the implemented system and his operating environment. In this paper we present an approach to automate scrubbing using failure prediction, though the use of both FPGA device health, from internal sensors data, and external environmental conditions. This solution will not only relieve the designer from the scrubbing specification, but also reduces the device’s power consumption and scrubbing intrusiveness.

Keywords

dependability, SEU, FPGA, failure prediction, embedded systems

Subject

Hardware Dependability

Conference

Latin-American Symposium on Dependable Computing (LADC 2016) 2016