CISUC

FIRED – Fault Injector for Reconfigurable Embedded Devices

Authors

Abstract

Reconfigurable embedded devices built on SRAM-based Field Programmable Gate Arrays (FPGA) are being increasingly used in critical embedded applications. However, the susceptibility of such memory cells to Single Event Upsets (SEU) requires the use of fault tolerant designs, for which fault injection is still the most accepted verification technique. This paper describes FIRED, a fault injector targeted at SRAM-based FPGAs for dependability evaluation of critical systems. This tool is able to perform hardware fault injection in real-time, by inserting bitflips at the SRAM cells through partial dynamic reconfiguration. These faults may produce errors in the design of the VHDL or Verilog modules deployed in the FPGA. A case study of a fault injection campaign in a PID-based cruise control system is used to evaluate the capabilities of FIRED, namely its capacity of injecting faults while a physical application is being controlled.


Keywords

dependability, fault injection, embedded systems, FPGA, SEU

Subject

An FPGA fault-injector

Related Project

CECRIS – CErtification of CRItical Systems

Conference

The 21st IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2015), November 2015

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Cited by

Year 2019 : 1 citations

 Fuchs, C.M., Fault-tolerant satellite computing with modern semiconductors, PhD Thesis, Faculty of Science. Leiden University, 2019-12-17, isbn:9789402817669, http://hdl.handle.net/1887/82454

Year 2018 : 1 citations

 Igor Villalta, Unai Bidarte, Julen Gómez-Cornejo, Jaime Jiménez, Jesús Lázaro, SEU emulation in industrial SoCs combining microprocessor and FPGA, Reliability Engineering & System Safety, Volume 170, 2018, Pages 53-63

Year 2017 : 2 citations

 Tingting Yu, Lei Chen, Xuewu Li, Shuo Wang, and Jing Zhou, "Critical-Bitstream-Based SEU Injection and Validation for Xilinx SRAM-Based FPGAs," International Journal of Electrical Energy, Vol. 5, No. 1, pp. 29-33, June 2017. doi: 10.18178/ijoee.5.1.29-33

 Yu, Tingting, et al. "Analyzing the Single Event Upset Sensitivity of Digital Clock Manager in Virtex-5 FPGA." Proceedings of the 6th International Conference on Informatics, Environment, Energy and Applications. ACM, 2017.